Analog Bits to Demonstrate Pinless PLL and Sensor IP in TSMC N4 and N5 Processes at TSMC 2022 North America Open Innovation Platform® Ecosystem Forum

Sunnyvale, CA, October 25, 2022 –Analog Bits (www.analogbits.com), the industry’s leading provider of low-power mixed-signal IP (Intellectual Property) solutions will be demonstrating silicon data for their Core Voltage Powered PLL and PVT Sensor at TSMC 2022 North America Open Innovation Platform (OIP) in both TSMC N4 and N5 process technologies. This development is part of Analog Bits’ broadening portfolio of Mixed Signal IP in TSMC N4 and N5 processes. This technology is also being developed in N3E and preliminary design kits are available now.

“Analog Bits’ patented Core-Powered designs are disruptingly innovative IP for our industry that enable placement anywhere on a chip without requiring external power supply pins, and without compromise in analog performance metrics. This key differentiator for advanced IPs optimizes performance, clocking power and system costs,” said Mahesh Tirupattur, Executive Vice President at Analog Bits. “Customers can now integrate an analog macro like a digital gate and the macro cleans the supply and pumps it at the point of use. We are pleased to show silicon demonstration of this breakthrough technology at TSMC 2022 NA OIP Ecosystem Forum.”

About Analog Bits

Founded in 1995, Analog Bits, Inc. is the leading supplier of mixed-signal IP with a reputation for easy and reliable integration into advanced SOCs. Our products include precision clocking macros, Sensors, programmable interconnect solutions such as multi-protocol SERDES and programmable I/O’s. With billions of IP cores fabricated in customer silicon, from 0.35 micron to 3nm processes, Analog Bits has an outstanding heritage of “first-time-working” with foundries and IDMs.

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